1. Field of the Invention
The present invention relates to a multiple PLL oscillator and, more particularly, to a multiple PLL oscillator suitable as an oscillator requiring both a higher transmitting frequency and reduction of phase noise in a radar performing a scan in a multiple millimeter CW radar.
2. Description of the Related Art
The principle configuration of a PLL oscillator is, as shown in FIG. 11, that the phase of a signal of a reference frequency fr and the phase of an output signal of a frequency divider 4 as a loop feedback signal are compared with each other by a phase comparator 1, the result is integrated and converted to a voltage signal by a low pass filter 2, and a voltage controlled oscillator 3 is controlled by the voltage signal. A part of an output of the voltage controlled oscillator 3 is divided by the frequency divider 4 to 1/N, the resultant is supplied as a signal to be compared to the phase comparator 1. The frequency-divided output frequency is compared with the reference frequency fr, thereby obtaining a PLL oscillator output of a desired frequency fout (=frxc3x97N). A multiple PLL oscillator obtaining a number of oscillation frequency outputs by changing the dividing number N of frequency is constructed.
From viewpoints of making the device simpler, making the band of an operation frequency wider, shortening time required for an oscillation frequency of a PLL circuit to reach a desired frequency (lock-up time), and the like in the actual configuration of a PLL oscillator, various PLL oscillators have been proposed.
Particularly, as a PLL oscillator adapted for use in telephones such as a mobile telephone and a portable telephone, a radio receiver, and a transceiver, having a relatively simple circuit configuration, realizing an oscillation output which is a high frequency, simultaneously, capable of varying an output frequency with short lock-up time and narrow frequency interval (frequency step), a PLL circuit as shown in FIG. 12 has been proposed (Japanese Unexamined Patent Application No. Hei-9-64734).
In the PLL circuit shown in FIG. 12, an oscillation output (oscillation frequency f1) of a first variable frequency oscillating circuit 16 and an oscillation output of a second variable frequency oscillating circuit 24 having an oscillation frequency f2 lower than that of the variable frequency oscillating circuit 16 are mixed by a mixer 59. A signal indicative of a sum of the oscillation frequencies of the variable frequency oscillating circuits 16 and 24 and a signal indicative of a difference between the oscillation frequencies are supplied as an oscillation output signal of the PLL circuit and an input signal of a feedback loop via filters 57 and 58. The feedback loop has a frequency divider 19 for dividing an oscillation signal of the frequency the difference. The phase of an output signal of the frequency divider 19 is compared with that of the signal of the reference frequency fr by a phase comparator 14. An output of the phase comparator 14 controls the oscillation frequencies of the variable frequency oscillating circuits 16 and 24 via a low pass filter 18.
The oscillation frequency of each of the variable frequency oscillating circuits 16 and 24 can be about the half of an output oscillation frequency fn of the PLL circuit, and the dividing number of the frequency divider can be reduced by feeding back an oscillation frequency difference fd between the variable frequency oscillating circuits 16 and 24 to the frequency divider 19 and mixing down a feedback signal of the loop to a lower frequency. Consequently, the lock-up time can be shortened and, simultaneously, the oscillation output can be changed at low frequency intervals also in a high frequency band.
In the PLL oscillating circuit shown in FIG. 12, a problem which occurs in a use where the circuit operates at the frequency interval of tens to hundreds kHz of the oscillation frequency in the millimeter wave band is not considered. For example, in a two frequency CW radar using millimeter waves which operates in a millimeter wave band, the frequency is switched at predetermined time intervals, and a distance and relative speed to an obstacle are detected on the basis of a Doppler shift and a phase difference of two received waves. Consequently, a reflected wave observed during a period in which an output frequency of a multiple PLL circuit is unstable due to increase in the lock-up time is handled as an indeterminate signal. The S/N ratio (=the signal of the radarxe2x88x92noise level) deteriorates by an amount corresponding to decrease in the total energy of the reflected wave. The more the frequency step is narrowed, the more the lock-up time increases, so that the two frequency CW radar using millimeter waves does not function at worst. In the case where the time of switching the frequency is increased so as to sufficiently observe the reflected wave, the frequency upper limit at the time of FFT (Fourier transform) in an A/D sampling period is suppressed, and an obstacle which moves at high speed cannot be detected.
In the proposed PLL circuit, the reference frequency is equal to or proportional to the frequency interval (frequency step) of the oscillation output. Therefore, the narrower the frequency interval is set, the narrower the loop band of the PLL becomes, so that the lock-up time to reach the desired frequency increases. In the case where a step frequency is hundreds kHz, the loop band of the PLL circuit is a faction of the frequency step so that the reference frequency component does not directly propagate to a voltage controlled oscillator, and lock-up time inversely proportional to the loop band is about tens xcexcsec.
In the PLL circuit shown in FIG. 12, the voltage controlled oscillating circuits 16 and 24 are disposed in parallel in a single PLL loop, and the oscillation frequency difference between the oscillating circuits computed by the mixer 59 is supplied as a loop feedback signal of the PLL circuit to the frequency divider 19. By increase in a loop gain K by reduction in the dividing number of frequency and shortened logic delay time of the frequency divider, the lock-up time is shortened.
Particularly, the PLL circuit is constructed by using the single reference frequency fr, and the output oscillation frequency fn of the PLL oscillating circuit is determined only by the reference frequency fr and the dividing number N of frequency of the frequency divider. Therefore, in the case of using the PLL circuit for a two waves millimeter wave radar of a millimeter wave band oscillation frequency and a step frequency of hundreds kHz, the dividing number of frequency becomes an enormous figure, so that it is impossible to main stability of the PLL circuit and shorten the lock-up time.
Since flicker caused by heat and external factors in the oscillating circuits 16 and 24 is absorbed as oscillation frequency variations in the PLL loop, an oscillation output in which the flicker is added and multiplied is observed. When two voltage controlled oscillators are constructed in the PLL loop, it is estimated that the state is similar to a state where a single feedback system has a plurality of oscillators, an oscillation like a double pendulum movement occurs, and the lock-up time becomes longer than lock-up time calculated from a loop band and a loop gain.
Further, since ratios of change of the oscillation frequencies f1 and f2 with respect to a control voltage Vc of the two voltage controlled oscillating circuits 16 and 24 are different from each other, to realize the PLL oscillating circuit, the ratios of change of the voltage controlled oscillating circuits 16 and 24 with respect to the control voltage Vc have to be constant and the frequency difference has to increase monotonously. Since the PLL loop performs a feedback control only on the frequency difference, even when the PLL operation is normally performed in the PLL loop, the frequency step of the oscillation frequency is not always correct. Generally, a voltage controlled oscillating circuit controls a depletion-layer capacitance of a structure of a semiconductor diode to specify the oscillation frequency. In an oscillating circuit in a millimeter wave band, in consideration of existence of stray capacitance, heat, and external factors which cannot be expressed in numerical values, it is difficult to make the change ratio difference between the oscillation frequency and the control voltage increase monotonously.
Since main targets of the PLL oscillating circuit of FIG. 12 are telephones such as a mobile telephone and a portable telephone, radio receivers, and transceivers, there is a tendency that the dividing number of frequency is increased to widen the variable range of the oscillation frequency. Consequently, the logic delay time in the frequency divider in the PLL loop is long, and it is also a factor of increasing the lock-up time.
An object of the invention is therefore to realize a multiple PLL oscillator having an oscillation output in a millimeter wave band and a simple configuration, with shortened lock-up time realized by decreasing the dividing number of frequency of a frequency divider provided for a PLL loop.
Another object of the invention is to realize a multiple millimeter CW radar for a vehicle, using a signal in a millimeter band, using a signal for generating signals of a plurality of frequencies having a relatively small transmission frequency difference (step frequency) at a predetermined interval, economically constructed, and operating stably.
To achieve the object, a multiple PLL oscillator of the invention includes: a plurality of reference frequency sources; a switch for selecting one of outputs of the plurality of reference frequency sources; a feedback loop circuit; a phase comparator for comparing the phase of a signal of a reference frequency selected by the switch with that of a signal from the feedback loop circuit; a voltage controlled oscillator controlled by an output of the phase comparator; a mixer for mixing an output of the voltage controlled oscillator with an output signal of a locked reference frequency source of another locked frequency; and an output unit for outputting an upper side band frequency of the mixer as an output. The feedback loop circuit has a frequency divider for receiving a lower side band frequency of the mixer and dividing the frequency of the input signal.
The multiple PLL oscillator of the invention includes: a plurality of reference frequency sources; a switch for selecting one of outputs of the plurality of reference frequency sources to thereby obtain a signal of a reference frequency; and a frequency synthesizer for setting a signal selected by the switch as a reference frequency. The frequency synthesizer is constructed to generate an oscillation output of the frequency corresponding to each of the plurality of reference frequency sources.
In the multiple PLL oscillator according to the invention, a plurality of output frequencies in the millimeter wave band having a frequency step are switched and output in a short period, and the frequency step is realized by switching operation of the switch for the plurality of reference frequency sources irrespective of a frequency divider. The frequency difference of the reference frequency sources is used, and signals indicative of sum and different of frequencies obtained by the mixer are used as an output signal of the multiple PLL oscillator and a loop feedback signal of the PLL loop, respectively, so that the dividing number of frequency of the frequency divider is decreased, and widening of the loop band, increase in the loop gain, and shortening of the lock-up time of the PLL circuit can be realized. Specifically, the lock-up time of the PLL circuit is proportional to a damping factor xcex6. The damping factor xcex6 is expressed as follows   ζ  =                    1        2            ⁢                        N                      τ            ⁢                          xe2x80x83                        ⁢            K                                =          1              2        ⁢                  xe2x80x83                ⁢        T        ⁢                  xe2x80x83                ⁢        ω        ⁢                  xe2x80x83                ⁢        n            
where N denotes the dividing number of frequency of the frequency divider, K denotes a loop gain, xcfx84 denotes a time constant of a low pass filter, and xcfx89n indicates a natural angular frequency. By decreasing the dividing number N of frequency, the lock-up time can be shortened.
As a result, by also forming the oscillator of a high frequency band of millimeter waves and the like in the form of a PLL circuit, various characteristics such as physical processing precision and a temperature characteristic accompanying disturbance can be controlled, so that the high frequency output signal of millimeter waves and the step frequency can be stably set with high precision. Particularly, a multiple CW oscillator for periodically stepping a frequency in short time is realized in a millimeter radar employing a two frequency CW radar system, and the stability of an output signal is increased. Consequently, improvements in various performances of the radar such as detected distance and angular information are realized, and a stable, high-performance, and cheap CW radar can be achieved.
These and objects, feature and advantages of the present invention will become more apparent in view of the following detailed description of the preferred embodiments in conjunction with the accompanying drawings.